With development of semiconductor technology, semiconductor devices are reduced in size. For example, as CMOS devices shrink to 45 nm, the gate dielectric materials may have an equivalent-oxide-thickness (EOT) of about 1 nm. High-k dielectric materials have been investigated to replace conventional gate oxide layers due to excellent current-leakage reduction seen when using the high-k dielectric materials at the same EOT. For devices small in size, it is desirable to use gate structure having a metal gate and high-k dielectric layer, instead of using polysilicon gate and low-k silicon oxide dielectric layer.
Conventional methods for forming metal gates include a gate-first process, and a gate-last process. In a gate-last process, a dummy gate is deposited and then removed after silicide formation at source/drain regions. Metals may then be filled to form a metal gate. Problems arise, however, because an undesired interfacial oxide layer is formed on the exposed surface after an NMOS (or PMOS) dummy gate is removed. This oxide layer is hard to remove because an aluminum (Al) film is exposed at the PMOS (or NMOS) region. Aluminum (Al) can be etched by both acid and alkali. Conventional etching processes used to remove interfacial oxide may also remove the PMOS Al and cause PMOS Al loss.
Existing methods for forming a metal gate structure in CMOS devices are shown in FIGS. 1-8. In FIG. 1, a semiconductor substrate 100 can include a region A (e.g., for forming an NMOS therein) and a region B (e.g., for forming a PMOS region). The semiconductor substrate 100 also includes an isolation region 110 for separating doped regions of the transistors.
In FIG. 2, polysilicon dummy gate structures 120a and 120b are formed on the semiconductor substrate 100. The polysilicon dummy gate structure 120a, associated with the region A for forming an NMOS transistor, includes a high-k dielectric layer 121a and a polysilicon dummy gate 122a. This defines the size and position of subsequently formed metal gate structure of the NMOS transistor. The polysilicon dummy gate 122a is to be replaced by a metal gate of the NMOS transistor.
The polysilicon dummy gate structure 120b, associated with the region B for forming a PMOS transistor, includes a high-k dielectric layer 121b and a polysilicon dummy gate 122b. This defines the size and position of subsequently formed metal gate structure of the PMOS transistor. The polysilicon dummy gate 122b is to be replaced by a metal gate of the PMOS transistor.
In FIG. 3, source region S1 and drain region D1 for an NMOS transistor are formed in region A. Source region S2 and drain region D2 for a PMOS transistor are formed in region B. Source regions and drain regions can be formed by various ion implantations in the substrate 100, depending on the types of each MOS transistor to be formed.
In FIG. 4, a dielectric layer 130 is formed covering the semiconductor substrate 100. The dielectric layer 130 is flushed with the polysilicon dummy gate structures 120a and 120b. The dielectric layer 130 is formed by depositing a dielectric material, followed by a chemical mechanical polishing (CMP) process.
In FIG. 5, the polysilicon dummy gate 122b is removed by a wet etching process to form an opening 140. A metal gate is subsequently formed in the opening 140. When forming the opening 140 and the metal gate for the PMOS transistor, the region A for forming NMOS is covered by a protective layer (not illustrated in the figure). The protective layer is formed by standard photolithography.
An interfacial oxide layer 150 may be formed in the opening 140 and on the high-k dielectric layer 121b during or after removal of the polysilicon dummy gate 122b. The interfacial oxide layer 150 may also be formed during previous formation of the polysilicon dummy gate 122b by polysilicon oxidization, often at high temperatures.
In FIG. 6, the interfacial oxide layer 150 is removed. The high-k dielectric layer 121b is exposed. A metal gate 160 is formed on the high-k dielectric layer 121b for the PMOS transistor. The metal gate 160 includes a multi-layered metal. The multi-layered metal includes a top layer and a work function layer. The top layer may be formed by aluminum. The PMOS transistor is then formed including a gate structure with metal gate 160 on the high-k dielectric layer 121b. 
In FIG. 7, once the metal gate structure has formed for the PMOS transistor, the protective layer on the polysilicon dummy gate 122a for NMOS transistor is removed from region A. A second protective layer (not illustrated in the figure) is formed to cover and protect the formed metal gate structure of the PMOS transistor in region B. The second protective layer is formed by photolithography.
An opening 170 is formed after removal of the polysilicon dummy gate 122a in region A for the PMOS transistor. Likewise, an interfacial oxide layer 180 is formed at the bottom of the opening 170.
In FIG. 8, after the interfacial oxide layer 180 is removed, a metal gate 190 is formed for the NMOS transistor. The metal gate structure for NMOS transistor therefore includes the metal gate 190 on the high-k dielectric layer 121a. 
As described above, photolithographic processes are used at least twice to cover one of regions A and B, when processing the other of regions A and B. Generally, photolithographic processes involve complex alignment techniques with high manufacturing cost. However, if the photolithographic processes were not used, the removing of interfacial oxide layer in the NMOS transistor will unduly damage the top layer of the already-formed metal gate of the PMOS transistor.
Thus, there is a need to overcome these and other problems of the prior art and to provide CMOS devices and fabrication methods without using photoresists as protective layers and without unduly damaging the surrounding structures that are formed in a CMOS process flow.